This invention relates to the field of semiconductor processing technology, and specifically to the field of custom or semi-custom fabrication of semiconductor chip packages or integrated circuit chips. In the present context, the term custom or semi-custom refers to microelectronics apparatus having devices, interconnections, etc. preformed in a regular or predetermined pattern, and interconnected, or not, as required for a custom use. Examples of such semi-custom apparatus includes master slice and master image wafers, and gate arrays. This invention may be used in the fabrication of integrated circuit chips to make electrical connections between the circuits on the chip, or in the fabrication of semiconductor chip packages to make electrical connections between integrated circuit chips thereon.
It is current practice for manufacturers to fabricate circuits on an integrated circuit chip wafer to the point where the only remaining processing steps are the formation of metallization layers to electrically connect the circuits. This partially completed wafer is then placed in inventory until it is sold to the ultimate customer as a semi-custom integrated circuit. The integrated circuit is then customized with the specification of particular metallization masks and the formation of the specific metallization layers which electrically connect the circuits to respond in the manner desired by the customer. A computer aided design program may be used to personalize the integrated circuits and to aid in defining or forming the final metallization mask, as is well known in the industry.
The time, effort and expense required to produce these metallization layer masks is significant, because each of the several metallization layer masks must be custom designed for each different type of integrated circuit or semiconductor chip package. This inherently leads to problems in design, prototype fabrication, manufacture, and testing, and each of these problems must be solved for each semi-custom circuit or package. In addition, the integrated circuit wafer or semiconductor chip package is at a higher risk of being damaged during the last processing steps needed to personalize the connections because each of the multiple step metallization processes is unique for each different semi-custom circuit. Another problem and added expense is the difficulty in producing satisfactory test devices that adequately test each circuit without first fabricating an entire mask. Thus, if any slight modifications in design are indicated after prototypes are produced, an entirely new mask must be produced, the fabrication processes must be repeated, and the test apparatus or program must be redesigned.
In accordance with the foregoing, it is an object of the present invention to provide a microelectronics apparatus, such as an integrated circuit chip or a semiconductor chip package, and a method for interconnecting wiring planes thereon.
It is another object of the present invention to provide a microelectronics apparatus and method of making it that eliminates the necessity of fabricating a unique set of metallization masks for each different semi-custom apparatus.
It is a still further object of the present invention to permit the manufacturer of the microelectronics apparatus to include multiple, connected wiring planes that may subsequently be personalized with a minimum of processing steps.
It is a still further object of the present invention to be able to produce prototype and final semicustom microelectronics apparatus without having to produce an entirely new mask if design changes are indicated.